Simulation of power consumption in Low-Dropout Voltage Regulators in 90 nm technology
M. manouchehri, Farzin Emami, Mohammad Hossein Sajadnia
A regulator design model is studied and simulated by using a dynamic bias technique. A dynamic bias boosting circuit consists of three parts: detector, amplifier and bias boosting circuit. The above Regulator is presented using CMOS 90 nm process and the obtained results will be examined with other existing technologies. The function of the diagram will be considered in this way that as soon as the slightest change is seen in output voltage; these changes will be transferred to the detector circuit through nodes Vn and Vp. The detector circuit makes sense of these changes and according to the type of detection, holds its output in the supply voltage situation or ground situation and will transfer it to the input of amplifier circuit. The amplifier circuit will work as an inverter and the detector's output will be appeared reversely in its output. The output of amplifier circuit is transmitted to the input of bias boosting circuit. This circuit, by increasing current, results in an increase in the regulated current in a short moment and returns the changes of regulator output voltage to the normal mode. In the discussed regulator, we reduced the power consumption using dynamic bias current to .5 mw and to some extent improved the line and load-transient response. The Technique of increasing the dynamic bias current in LDO design effectively improves the linear and load transmission response and leads to the creation of a precise and affecting voltage in the regulator's output and will be very effective in portable applications where an accurate and noiseless power supply is require.